1. Field of the Invention
The present invention relates to semiconductor technology, and in particular to methods for forming a high voltage (HV) semiconductor device having shallow trench isolation (STI).
2. Description of the Related Art
Power management integrated circuit (PMIC) is presently primarily applied to Bipolar-CMOS-LDMOS (BCD) structures. Complementary metal oxide semiconductor (CMOS) transistors may be used in digital circuits, bipolar transistors may be used for driving high current, and lateral diffused metal oxide semiconductor (LDMOS) transistors have high voltage handling capacity. The trends of power saving and high speed performance affect the LDMOS structure. LDMOSs with lower leakage and on-resistance (RDSon) have been developed by semiconductor manufacturers. RDSon is an important factor which affects the power consumption of the conventional LDMOS device.
Breakdown voltage is taken into account when the low on-resistance device is developed. The LDMOS devices are developed in various structures or by increasing the device size thereof to withstand the high breakdown voltage. However, since the device size is increased, the on-resistance is increased as well.
Accordingly, there exists a need in the art for development of a novel method for forming a semiconductor device that is capable of mitigating or eliminating the aforementioned problems.